1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit fabrication technology and, more particularly, to a method of forming an isolation oxide layer in a semiconductor integrated circuit (IC) device.
2. Description of the Related Art
As is well known in the art, a semiconductor IC device employs in general a metal oxide semiconductor field effect transistor (MOSFET) as a unit transistor. Due to a reduced design rule and increased integration degree of the IC device, the size of the MOSFET also becomes smaller and smaller. Such a trend towards smaller MOSFET size may require a decrease in gate effective channel length and thereby invite several problems such as punch through phenomenon, short channel effect, etc.
In order to solve the above problems, various approaches have been introduced and studied in the art. One of them is a selective epitaxial growth (SEG) technique. For example, an anisotropic SEG technique has been widely used to form an epitaxial layer for elevated source/drain.
In a typical SEG process, an oxide layer is deposited on a silicon substrate and selectively etched to expose active regions of the silicon substrate. A silicon layer is then grown on the exposed regions of the silicon substrate. As a result, the silicon layer forms a number of active regions physically separated and electrically isolated by the oxide layer.
This isolation oxide layer may be formed traditionally by chemical vapor deposition (CVD) technique. However, the CVD oxide layer may have relatively poor layer quality such as integrity, uniformity, and defects, thereby causing a drop in isolation properties.